test_全串行15阶FIR滤波器程序.docVIP

--- TEST 文件 -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.all;--使用有符号数运算 USE ieee.numeric_std.ALL; --声明文件操作所需的程序包 use ieee.std_logic_textio.all; use std.textio.all; ENTITY tst IS END tst; ARCHITECTURE behavior OF tst IS COMPONENT Fir8Serial PORT( rst : IN std_logic; clk : IN std_logic; Xin : IN std_logic_vector(11 downto 0); yout : OUT std_logic_vector(28 downto 0)); END COMPONENT; --输入信号 signal rst : std_logic := 0; signal clk : std_logic := 0; signal Xin : std_logic_vector(11 downto 0) := (others = 0); --输出信号 signal yout : std_logic_vector(28 downto 0); -- 定义时钟周期 constant clk_period : time := 0.625 us; --16KHz --添加读滤波器输出数据屏蔽信号 signal Hide_out: std_logic := 0; --添加计数器信号，用于对输入时钟分频，产生1/8时钟频率的数据输入时钟 signal count: std_logic_vector(2 downto 0):=(others=0); BEGIN --实例化测试模块 uut: Fir8Serial PORT MAP ( rst = rst, clk = clk, Xin = Xin, yout = yout ); rst =1 after 20 ns; --上电复位20ns后开始工作 Hide_out =1 after 10 us; --屏蔽掉前2个0值滤波器输出数据 --产生系统时钟信号 clk_process :process begin clk = 0; wait for clk_period/2; clk = 1; wait for clk_period/2; end process; --3位计数器，实现8分频 process(rst,clk) begin if rst=0 then count=(others=0); elsif rising_edge(clk) then count=count+1; end if; end process; --从文本文件中读取数据做为输入信号 process variable vline:LINE; variable v: std_logic_vector(11 downto 0); --需要根据文件存放目录，修改下面语句的文件路径 file invect:text is ..\E4_7_Bin_s.txt; --进行白噪声输入数据仿真时，注释掉该行上面一行的语句，同时取消该行下面一行的语句注释 --file invect:text is D:\DuYong\Filter_VHDL\FirFullSerial\E4_7_Bin_noise.txt; --file invect:text is D:\DuYong\Filter_VHDL\FirHalfSerial\E4_7_Bin_s.txt; --file invect:text is D:\DuYong\Filter_VHDL\FirHalfSerial\E4_7_Bin_noise.txt; begin wait until rising_edge(count(2)); if not (ENDFILE(invect)) then