集成电路设计preface教程分析.ppt

* * 武汉-中芯国际，国家国家自主创新示范区-东湖高新区 * 3G,LTE, WiMax，MESH Sensor Networks，Smart Dust，Internet of Things，Smart Planet SOC,MEMS (Micro Electro Mechanical systems ) * * * * TTL had a higher integration density than ECL Power – puts an upper limit on the number of gates that can be reliably integrated on a single die * * PMOS came first because of fab problems with NMOS NMOS next because of fab problems with CMOS (NMOS has speed advantage over PMOS due to carrier mobility) * * * * * * * * Staffing costs computed at $150K/staff year (in 1997 dollars) * * * * Here again, we’re focusing on schematic designs, trying to relate the concept of synthesis to something they’ve seen before. Here, we’re trying to show that synthesis is nothing new; engineers have always taken a “specification”, and made a circuit to implement that specification. * * During the synthesis process, trade-offs between area and performance are made. The predominant factor in this trade-off is the line delays. At the first pass, estimated timing is used. This has a wide range of tolerance and does not represent accurate representations of the final delays. This results in a conservative approach to performance in order to account for the lack of physical knowledge. A much more accurate estimation of the physical delays can be achieved by placing the components then extrapolating from the line of sight distance (), a reasonable prediction of the line delays. It is this view that provides the basis for Physical Synthesis. * Once a set of standard cells is created (usually hundreds) they can be used to construct an entire chip design. Using a net list generated and optimized from the synthesis process, the cells are placed according to their connection structure. Then using the net list, the router software makes the actual connections. Chips or large blocks contain 100,000’s of cells thus making the place and route process very complicated. * . * Static vs. dynamic Timing engine can be used by