第八章 状态机.pptVIP

第八章 状态机;状态机：设计时序电路 应 用：控制器 本 质：按功能将电路分解为不同状态，在 时钟控制下，电路在各个状态之间 进行转移，实现电路功能。 分 类：moore(摩尔）型，输出只和当前状 态有关，和输入无关。 mealy(米里）型，输出取决现态和 输入 ;8.1 状态机设计;二、状态转移图;以四进制计数器为例： 状态转移图 ;三、状态机vhdl描述;例1：四进制计数器 Library ieee; Use ieee.std_logic_1164.all; Entity counter_4 is port(clk:in std_logic); counter:out std_logic_vector(1 downto 0)); End counter_4; Architecture bhv of counter_4 is type state is (s0,s1,s2,s3); signal p_s,n_s:state; begin process(clk) ;Begin if clk’event and clk=‘1’ then p_s=n_s; end if; End process; Process(p_s) begin case p_s is when s0=counter=“00”; n_s=s1; when s1=counter=“01”; n_s=s2; when s2=counter=“10”; n_s=s3; when s3=counter=“11”; n_s=s0; End case; End process; End bhv; ;例2：BCD计数器 状态转换图 ;1 ------------------------------------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------------------- 5 ENTITY counter IS 6 PORT ( clk, rst: IN STD_LOGIC; 7 count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); 8 END counter; 9 ------------------------------------------------- 10 ARCHITECTURE state_machine OF counter IS 11 TYPE state IS (zero, one, two, three, four, 12 five, six, seven, eight, nine); 13 SIGNAL pr_state, nx_state: state; 14 BEGIN;15 ------------- Lower section: ----------------- 16 PROCESS (rst, clk) 17 BEGIN 18 IF (rst=1) THEN 19 pr_state = zero; 20 ELSIF (clkEVENT AND clk=1) THEN 21 pr_state = nx_state; 22 END IF; END PROCESS; 24 ------------- Upper section: ----------------- 25 PROCESS (pr_state) 26 BEGIN 27 CASE pr_state IS 28 WHEN zero = 29 count = 0000; 30 nx_state = one;;31 WHEN one = 32 count = 0001; 33 nx_state = two; 34 WHEN two = 35 count = 0010; 36 nx_state = three; 37 WHEN three = 38 count = 0011; 39 nx_state = four; 40 WHEN four = 41 count = 0100; 42 nx_state = five; 43 WHEN five = 44 count = 0101; 45 nx_state = six; 46 WHEN six = 47 count = 0110; 48 nx_state = s