VLSI与电子器件教学资料：6.4 Metal-insulator-semiconductor FET.pptVIP

advantage: high d-c input impedance , because applications: Switch * 6.4 Metal-insulator-semiconductor FET Metal-Oxide-Silicon FET (MOSFET) Polysilicon/多晶硅 accumulation layer/堆积层 flat band/平带 depletion layer/耗尽层 inversion layer/反型层 strong inversion/强反型 ionized acceptor/电离受主杂质 criterion/判据 neutral/中性的 surface potential/表面势 Debye screening length/德拜屏蔽长度 Oxide/氧化物 substrate/衬底 lithography/光刻 silicon oxide (SiO2)/氧化硅 threshold voltage/阈值电压/开启电压 ideal/理想的 intrinsic level (Ei)/本征能级 deposit/放置/淀积 tilt/倾斜 gradient/梯度 energy band bending/能带弯曲 6.4.1 Basic Operation and Fabrication A fabrication process for MOSFET P-type Si n+-type/diffusion扩散 SiO2 /oxidation氧化 Metal Substrate衬底 Lithography光刻 VG-VD=VT VG-VT=VDSAT Gate-controlled resister V G ID VT 6.4.1 Basic Operation and Fabrication An important parameter:Threshold voltage(阈值电压)VT VT is defined as the minimum gate voltage required to induce the channel. 6.4.1 Basic Operation and Fabrication Gate-controlled potential barrier 6.4.2 The ideal MOS capacitor (理想MOS电容器) Voltage -V +Q -Q ? Reference -q(-V)=qV The difference between M and S n :1022-23cm-3(for metal) n or p : 1019cm-3(for semiconductor) Charge state +qn or -qn (for metal) q(p-n+N+D-N-A) (for semiconductor) Thick charge layer Thin charge layer 6.4.2 The ideal MOS capacitor (理想MOS电容器) (1)Energy band q?F=Ei-EFs It implies no difference of the two work functions, no other initial charges within the oxide, and no current through the oxide. An electric field near the surface of semiconductor causes a bending of the bands. Hole accumulation (空穴堆积) ?(x) is defined as a potential at any point x relative to the bulk where the potential is taken to be the zero. Because the voltage V is negative, the energy level will rise by qV. Depletion(耗尽) Inversion(反型) ?s=0, -q?s=0, flat band(平带) ?s0, -q?s0, accumulation(堆积) ?s0, -q?s0, depletion(耗尽) ?s0, -q?s0, inversion(反型) ?(x): the potential at x; ?s=?(x=0): the surface potential; -q?(x): the extent of band bend at x; -q