EDA频率计 实验报告++.docVIP

EDA频率计 实验报告 library work; library std; library ieee; use ieee.std_logic_1164.all; entity cnt10 is port(clk:in std_logic; clr:in std_logic; ena:in std_logic; cq:out integer range 0 to 15; carry_out:out std_logic); end entity cnt10; architecture art of cnt10 is signal cqi:integer range 0 to 15; begin process(clk,clr,ena)is begin if clr=1 then cqi=0;elsif clkevent and clk=1 then if ena=1 then if cqi9 then cqi=cqi+1;else cqi=0; end if; end if; end if; end process; process(cqi) is begin if cqi=9 then carry_out=1;else carry_out=0;end if; end process; cq=cqi; end architecture art; Reg32: library work; library std; library ieee; use ieee.std_logic_1164.all; entity reg32b is port(load:in std_logic; din:in std_logic_vector(31 downto 0); dout:out std_logic_vector(31 downto 0)); end entity reg32b; architecture art of reg32b is begin process(load,din) is begin if loadevent and load=1then dout=din;end if; end process; end architecture art; Testctl: library work; library std; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity testctl is port(clk:in std_logic; tsten:out std_logic; clr_cnt:out std_logic; load:out std_logic); end entity testctl; architecture art of testctl is signal div2clk:std_logic; begin process(clk) is begin if clkevent and clk=1 then div2clk=not div2clk; end if; end process; process(clk,div2clk) is begin if clk=0 and div2clk=0 then clr_cnt=1 ;else clr_cnt=0; end if; end process; load=not div2clk;tsten=div2clk; end architecture art; 4:freq.vhd（顶层文件） library work; library std; library ieee; use ieee.std_logic_1164.all; entity freq is port(fsin:in std_logic; clk:in std_logic; dout:out std_logic_vector(31 downto 0)); end entity freq; architecture art of freq is component cnt10 is port(clk,clr,ena:in std_logic; cq:out std_logic_vector(3 downto 0); carry_out:out std_logic); end component cnt10; component reg32b is port(load:in std_logic; din:in std_