一种数字信号处理器中的高性能乘加器设计.pdfVIP

40 1 Vol40, No. 1 2010 2 Micr oelectr onics Feb. 2010 孙偲彦, 蒋剑飞, 毛志刚 ( , 200240) : 乘加操作是数字信号处理器( DSP) 的关键部分, 单位时间内 够完成乘加操作的数量是 衡量DSP 芯片性 的 一个重要指标提出了一种应用于通用数字信号处理器的乘加器设计方法, 在改进的Booth 编码结合Wallace 树压缩的基础上, 通过在部分积压缩时插入MAC 操作的加数, 减少符号位扩展, 实现了乘加操作的一步完成提出一种有效的结构实现通用信号数字处理其所 需的分数模式零检测饱和溢出控制舍入操作等异常处理功 ; 并对乘加器的速度面积功耗等 性 进行了分析 : 数字信号处理器; 乘加器; Booth 编码; 华莱士树压缩 + : N79 1 :A : 2010) Design of Efficient M ultiplierAccumulator for DSP SU N Siyan, JIAN G Jianfei, MAO Zhigang (School of Microelectronics , Shanghai Jiaotong University , Shanghai 200240, P . R . China) Abstract : Multiplieraccumulator (MAC) is the key unit in digital signal processing (DSP) . One of the most important parameters for DSP performance is the number of MAC operations in unit time. An efficient MAC design w as proposed for general DSP application. Based on modified Booth encoding and Wallace tree merging, multiplying and accumulating opera tions were accomplished simultaneously by merging addend in the Wallace tree and reducing sign extension. An efficient structure w as proposed to realize FRC , zerodetection, overflow control, and rounding for general application DSP. Final ly, analyses were made on the circuit for speed, size and power consumption reduction. Key words: Digital signal processing; Multiplieraccumulator; Booth encoding; Wallace tree merging EEACC: 1265 , , Booth [ 1, 2] 1 引言 Wallace Booth