FPGA数据发送与显示.docVIP

顶层主程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rslcd is Port(clock,rxin : in STD_LOGIC; resetin : in STD_LOGIC; rwo,rso,eo,txout : out STD_LOGIC; led:out std_logic_vector(7 downto 0); data_out : out STD_LOGIC_VECTOR(7 downto 0)); end rslcd; architecture Behavioral of rslcd is COMPONENT rs232 is Port(clk,rx,reset: in STD_LOGIC; tx : out STD_LOGIC; cnt : out integer range 0 to 31; dateout:out std_logic_vector(7 downto 0)); END COMPONENT; COMPONENT lcd is Port(clk : in STD_LOGIC; reset : in STD_LOGIC; cntin : in integer range 0 to 31; datein: in std_logic_vector(7 downto 0); rw,rs,e : out STD_LOGIC; data : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; signal datax : std_logic_vector(7 downto 0); signal cnt_s : integer range 0 to 31; BEGIN u1:rs232 PORT MAP(clk=clock,reset=resetin,rx=rxin,tx=txout,dateout=datax,cnt=cnt_s); u2:lcdPORTMAP(clk=clock,reset=resetin,rw=rwo,e=eo,rs=rso,data=data_out,datein=datax,cntin=cnt_s); led=datax; end behavioral; 接收程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rs232 is Port(clk,rx,reset: in STD_LOGIC; tx : out STD_LOGIC; cnt : out integer range 0 to 31; dateout:out std_logic_vector(7 downto 0)); end rs232; architecture Behavioral of rs232 is signal div,div3:std_logic_vector(11 downto 0); signal clk1,aw1,clk3 :std_logic; signal date_out: std_logic_vector(9 downto 0); Signal busy :std_logic ; Signal Enable :std_logic :=0; Signal Hold :std_logic :=0; Signal N :std_logic_vector(0 to 2) :=000; begin busy=Enable and Hold; process(reset,rx) begin if reset=0 then Hold=0; elsif falling_edge(rx) then Hold=1; end if; end process; process(clk) begin if reset=0 then aw1=0; div=(others=0); elsif rising_edge(clk) then div =div+1; if div=519 then div=(others=0); aw1=1;