锁相技术译文翻译：数字混合PLL频率合成器开关特性分析.doc

锁相技术译文翻译 英文原名： Analysis of Switching Characteristics of the Digital Hybrid PLL Frequency Synthesizer 译文：数字混合PLL频率合成器的开关特性分析 年纪专业：____________________ 姓名：_____________ 学号：_______________ 年 月 日 英文 中文 Analysis of Switching Characteristics of the Digital Hybrid PLL Frequency Synthesizer Heung-Gyoon Ryu, Member, IEEE, and Hyun-Seok Lee Abstract—In this paper, we address the switching characteristics of the digital hybrid phase-locked loop (DH-PLL) frequency synthesizer. We analyze the effects of the division ratio for frequency synthesis and the component errors of a DH-PLL circuit on the switching performance. Gain variation, offset error generated in a digital-to-analog converter, and frequency drift error of voltage-controlled oscillation due to temperature and aging are considered as the errors of the circuit components. From the simulation results, the conventional charge-pump PLL system has much different switching time for the change spacing of the frequency synthesis. On the contrary, the variation of the switching time is not so great in the DH-PLL system when the error magnitude does not exceed the ?4 least significant bit error. To guarantee the required minimum switching speed, it is important that the tolerable error range be determined. Index Terms—Device error and switching, digital hybrid phase-locked loop (DH-PLL), frequency synthesizer. I. INTRODUCTION HIGH-SPEED switching is one of the most important characteristics in frequency synthesizers. In 1999, Abou El-Ela proposed a method in which an additional input to a voltage control oscillator (VCO) is required to get higher switching speed in a phase-locked loop (PLL) frequency synthesizer [1]. This is a structure to provide VCO with an additional input of the sawtooth wave using a digital-to-analog (D/A) converter. Whenever frequency is synthesized, the waveform generator with the most optimum slope and duration is required. Therefore, the complicated design and the exact synchronization