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472 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 5, OCTOBER 2000 Scheduling with Bus Access Optimization for Distributed Embedded Systems Petru Eles, Member, IEEE, Alex Doboli, Student Member, IEEE, Paul Pop, and Zebo Peng, Member, IEEE Abstract—In this paper, we concentrate on aspects related to system-level synthesis process. Surveys on this topic can be the synthesis of distributed embedded systems consisting of pro- found in [1]–[6]. grammable processors and application-specific hardware compo- An important characteristic of an embedded system is its per- nents. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of con- formance in terms of timing behavior. In this paper, we con- trol. Our goal is to derive a worst case delay by which the system centrate on several aspects related to the synthesis of systems completes execution, such that this delay is as small as possible; consisting of communicating processes, which are implemented to generate a logically and temporally deterministic schedule; and on multiple processors and dedicated hardware components. In to optimize parameters of the communication protocol such that such a system, in which several processes communicate with this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the each other and share resources like processors and buses, sched- overall performance and, specially, how the requirements of such uling of processes and communications is a facto