PLL驱动DDS的低相噪小步进LFM信号源设计.pdfVIP

第38卷 第2期 电 子 器 件 Vol．38　 No．2 2015年4 月 ChineseJournal of Electron Devices Apr. 2015 Design of a LFM Signal Source with Low Phase Niose and Small Frequency Step Based on PLL Driver DDS∗ ∗ WANG Wencai,CHEN Changming ,HUANG Gang (School of Communication Engineering,Chengdu University of Information Technology,Chengdu 610225,China) Abstract:The method of generating and implementing a kind of linear frequency modulation(LFM)radar signals with low phasenoiseisintroduced.The 1GHzPLLisdesignedasDDS’sclockdrivercircuitusing HMC704 control VCO by analyzing the spectrum of the output signal and the DDS spurious. The loop filter and AD9910 hardware circuit is also optimized in order to improvethephase noise and spurious.Theregister parametersiscalculated and SPI bus timing is analyzed,DDS and PLL is configured high-speedy by FPGA. Experimental results show that the - - LFM source output amplitude greater than 3 dBm,frequency step is 1 kHz,the phase noise is better than 103 dBc/ Hz@1kHz,the indicators meet the practical engineering requirements. + Key words:frequency source;LFM;PLL DDS;AD9910;HMC704 - EEACC:1230　 　 　 　 doi:10.3969/j.issn.1005 9490.2015.02.024 PLL驱动DDS 的低相噪小步进LFM信号源设计∗ ∗ 王文才,陈昌明 ,黄　 刚 (成都信息工程学院通信工程学院,成都 610225) 摘　 要:介绍了一种低相噪线性调频(LFM)雷达信号源的产生和实现方案。 通过分析 DDS输出信号频谱和杂散,采用 HMC704控制VCO的方法设计了1GHz 的锁相环路(PLL)作为DDS的时钟驱动电路,并对环路滤波器和AD9910硬件电路优 化设计改善杂散和相噪性能。 通过计算寄存器参数和分析SPI总线时序,利用FPGA对DDS和PLL高速配置。 最后给出了 -