天津大学《数字电子技术》课件vga.pptxVIP

VGA显示

FPGA程序设计;VGA接口;对应管脚与显示原理;Signaltimingsfora640-pixelby480rowdisplayusinga25MHzpixelclockand60Hzverticalrefresh

VTs=16.7ms，也就是场刷新率为1000/16.7=60Hz;`timescale1ns/1ps

//ModuleName:vga_640x480

modulevga_dr#(parameterHA=16,HB=96,HF=48,HD=640,HT=800,

VA=10,VB=2,VF=33,VD=480,VT=525)

(inputwirevga_pclk,vga_rst,

outputwirevga_hsync,vga_vsync,vga_valid,

outputwire[11:0]vga_h_cnt,

outputwire[10:0]vga_v_cnt

);

reg[11:0]pixel_cnt;//每行640个像素点计数器，最大计到799

reg[10:0]line_cnt;//每屏显示480行的计数器，最大计数到524

reghsync,vsync;//行同步脉冲，场同步脉冲

always@(posedgevga_pclk,posedgevga_rst)

if(vga_rst)pixel_cnt=0;

elseif(pixel_cnt(HT-1))pixel_cnt=pixel_cnt+1;

elsepixel_cnt=0;;always@(posedgevga_pclk,posedgevga_rst)//行同步脉冲产生模块

if(vga_rst)

hsync=1;

elseif((pixel_cnt=(HD+HA-1))(pixel_cnt(HD+HA+HB-1)))

hsync=0;

elsehsync=1;

always@(posedgevga_pclk,posedgevga_rst)//行计数器

if(vga_rst) line_cnt=0;

elseif(pixel_cnt==(HT-1))

if(line_cnt(VT-1)) line_cnt=line_cnt+1;

else line_cnt=0;

always@(posedgevga_pclk,posedgevga_rst)//根据行计数器产生的场同步脉冲

if(vga_rst) vsync=1;

elseif((line_cnt=(VD+VA-1))(line_cnt(VD+VA+VB-1)))

vsync=0;

else vsync=1;;assignvga_hsync=hsync;//行同步脉冲

assignvga_vsync=vsync;//场同步脉冲

assignvga_valid=((pixel_cntHD)(line_cntVD));//显示有效信号

assignvga_h_cnt=(pixel_cntHD)?pi