硬件描述语言一.pptVIP

* 时延 * 时延可以细分为两种类型: 1) 语句间时延: 这是时延语句执行的时延。 2) 语句内时延: 这是右边表达式数值计算与左边表达式赋值间的时延。 * * 这个赋值中的时延意味着首先计算右边表达式的值, 等待5个时间单位，然后赋值 * Gate delay * * * * * Verilog中的操作类型 Logical Operators Bitwise Operators Reduction Operators Shift Operators Concatenation Operator Relational Operators Equality Operators Conditional Operator Arithmetic Operators * Logical Operators ? logical AND || ? logical OR ! ? logical NOT Operands evaluated to ONE bit value: 0, 1 or x Result is ONE bit value: 0, 1 or x A = 6; A B ? 1 0 ? 0 B = 0; A || !B ? 1 || 1 ? 1 C = x; C || B ? x || 0 ? x * Bitwise Operators ? bitwise AND | ? bitwise OR ~ ? bitwise NOT ^ ? bitwise XOR ~^ or ^~ ? bitwise XNOR Operation on bit by bit basis * Reduction Operators ? AND | ? OR ^ ? XOR ~ ? NAND ~| ? NOR ~^ or ^~ ? XNOR One multi-bit operand ? One single-bit result a = 4’b1001; .. c = |a; // c = 1|0|0|1 = 1 * Shift Operators ? shift right ? shift left Result is same size as first operand, always zero filled a = 4’b1010; ... d = a 2; // d = 0010 c = a 1; // c = 0100 * Concatenation Operator {op1, op2, ..} ? concatenates op1, op2, .. to single number Operands must be sized !! reg a; reg [2:0] b, c; .. a = 1’b 1; b = 3’b 010; c = 3’b 101; catx = {a, b, c}; // catx = 1_010_101 caty = {b, 2’b11, a}; // caty = 010_11_1 catz = {b, 1}; // WRONG !! Replication .. catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101 * Relational Operators ? greater than ? less than = ? greater or equal than = ? less or equal than Result is one bit value: 0, 1 or x 1 0 ? 1 ’b1x1 = 0 ? x 10 z ? x * Equality Operators == ? logical equality != ? logical inequality === ? case equality !== ? case inequality 4’b 1z0x == 4’b 1z0x ? x 4’b 1z0x != 4’b 1z0x ? x 4’b 1z0x === 4’b 1z0x ? 1 4’b 1z0x !== 4’b 1z0x ? 0 * Conditional Operator cond_expr ? true_expr : false_expr * Arithmetic Operators + - * / % … * Operator Precedence * 两种不同的赋值语句(Procedure) 非阻塞赋值 always @(posedge clk