第三章 组合逻辑电路的VHDL设计3-2.ppt

* TM Design of Programmable Logic System CS-SWPU * TM Design of Programmable Logic System CS-SWPU 4:1多路选择器的电路结构 00 01 10 11 s0 s1 a b c d y 0 1 0 1 0 1 s1 s0 a b c d y s1 s0 y(s1,s0) 0 0 a 0 1 b 1 0 c 1 1 d 常规的结构 library IEEE; use IEEE.std_logic_1164.all entity mux is port(a, b, c, d: in std_logic; s: in std_logic_vector(1 downto 0); y: out std_logic); end mux; architecture mux1 of mux is begin with s select y = a when “00”， b when “01”， c when “10”， d when “11”， ‘X’ when others; end mux1; 带三态特性的结构 library IEEE; use IEEE.std_logic_1164.all entity mux is port(a, b, c, d: in std_logic; s: in std_logic_vector(1 downto 0); y: out std_logic); end mux; architecture mux1 of mux is begin y = a when s= “00” else ‘Z’; y = b when s= “01” else ‘Z’; y = c when s= “10” else ‘Z’; y = d when s= “11” else ‘Z’; end mux1; 四、优先权编码器 什么是优先权编码器？ A0 A1 A2 A3 Y0 Y1 Valid 4:2 Priority A3 A2 A1 A0 Y1 Y0 Valid 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 - 0 1 1 0 1 - - 1 0 1 1 - - - 1 1 1 基于真值表的模型 Library IEEE; use IEEE.std_logic_1164.all; entity priority is port ( a: in std_logic_vector(3 downto 0); y: out std_logic_vector(1 downto 0); valid: out std_logic); end priority; architecture tru_table of priority is begin with a select y = “00” when “0001”, “01” when “001 -”, “10” when “01 - -”, “11” when “1 - - -”, “00” when others; valid = “1” when a(0)=‘1’ or a(1)=‘1’ or a(2)=‘1’ or a(3)=‘1’ else ‘0’; end tru_table; ‘-’会引起什么问题 ? 仿真波形 对‘-’的处理 use IEEE.numeric_std.all; architecture match of priority is begin y = “00” when std_match(a, “0001”) else “01” when std_match(a, “001 -”) else “10” when std_match(a, “01 - -”) else “11” when std_match(a, “1 - - -”) else “00”; valid = ‘1’ when a(0)=‘1’ or a(1)=‘1’ or a(2)=‘1’ or a(3)=‘1’ else ‘0’; end mactch; 注意此包的位置及其作用范围 更一般的模型 architecture orde