VHDL的任意整数且占空比为50.docVIP

VHDL的任意整数且占空比为50%分频代码 说明如下： 1.其中top file 为 division，其中的clk_com是比较的频率，用它来和分频后波形进行比较，便于观察， 2.any_enve为任意偶数分频文件 3.any_odd为任意奇数分频文件 4.是一个用于2进制与8进制的译码器，我用它来显示在数码管上当前到底是多少分频 5.以下代码在开发板上实验过，请大家放心使用，欢迎转载，但请注明出处，另外说明由于用的是quartus7.1编辑的，中间无法加中文注释，请大家慢慢读了；以下是代码： ------the top file of the design division library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity division is port (input : in std_logic_vector(7 downto 0); clk : in std_logic; clk_out : out std_logic; clk_com : out std_logic; led1: out std_logic_vector(6 downto 0); led2: out std_logic_vector(6 downto 0); led3: out std_logic_vector(6 downto 0)); end entity division; -------------------------------------------------- architecture freq of division is component decoder is----decoder port(bin : in std_logic_vector(2 downto 0); de : out std_logic_vector(6 downto 0)); end component; component any_even is----any_even division generic (data_width : integer := 8 ); port(input1 : in std_logic_vector(data_width-1 downto 0); clk_in : in std_logic; clk_out : out std_logic); end component any_even; component any_odd is-----any_even division generic (data_width : integer := 8); port(input2 : in std_logic_vector(data_width - 1 downto 0); clk_in : in std_logic; clk_out : out std_logic); end component any_odd; signal temp1,temp2 : std_logic; begin u1: decoder port map(bin=input(2)input(1)input(0),de=led1); u2: decoder port map(bin=input(5)input(4)input(3),de=led2); u3: decoder port map(bin=0input(7)input(6),de=led3); u4: any_even port map(input,clk,temp1); U5: any_odd port map(input,clk,temp2); process(clk,input) begin if input(0)= 0 then clk_out = temp1; else clk_out = temp2; end if; end process; clk_com = clk; end architecture freq; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity any_even is generic (data_width : integer := 8 ); port(input1 : in std_logic