74ALVC74D,112,74ALVC74PW,118,74ALVC74PW,112,74ALVC74BQ,115,74ALVC74D,118, 规格书,Datasheet 资料.pdfVIP

INTEGRATED CIRCUITS DATA SHEET 74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification 2003 May 26 Supersedes data of 2003 Jan 24 芯天下--/ Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; 74ALVC74 positive-edge trigger FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V The 74ALVC74 is a dual positive-edge triggered, D-type • Complies with JEDEC standard: flip-flop with individual data (D), clock (CP), set (SD) and JESD8-7 (1.65 to 1.95 V) reset (RD) inputs and complementary Q and Q outputs. JESD8-5 (2.3 to 2.7 V) The set and reset are asynchronous active LOW inputs JESD8B/JESD36 (2.7 to 3.6 V). and operate independently of the clock input. Information • 3.6 V tolerant inputs/outputs on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs • CMOS low power consumption must be stable one set-up time prior to the LOW-to-HIGH • Direct interface with TTL levels (2.7 to 3.6 V) clock transition for predictable operation. • Power-down mode Schmitt-trigger action in the clock input makes the circuit • Latch-up performance exceeds 250 mA highly tolerant to slo