Layout Optimizations for Double Patterning （双模式的布局优化）.pdfVIP

Layout Optimizations for Double Patterning Lithography † David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho , and Yongchan Ban Dept. of ECE, The University of Texas at Austin, Austin, TX 78712 †IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 {dpan, jsyang, kyuan}@, minsikcho@, ycban@ Abstract—Lithography process has become one of the most SADP, but requires more accurate overlay control to align two fundamental limitations for 22nm technology node because of the exposures [12]–[15]. LFLE works by freezing the developed following reasons: 1) combining immersion and computational resist pattern of the first exposure, then adding a second resist lithography, which is the most advanced lithography scheme, may not be enough to be used for 22nm patterning, 2) EUV layer immediately on top for the second exposure. The resist (Extreme Ultra-Violet) lithography may not be available for pattern is etched at one time after developing. LFLE uses mass production in the near future. As a practical solution, fewer processing steps [16] [17]. SADP works by depositing a pitch doubling technique known as double patterning lithography spacer layer over the chip covering all hard mask features. The (DPL) has become a strong candidate for 22nm lithography covered layer is selectively etched away leaving two sidewalls process. Since layout decomposition in DPL plays an important role in addressing the patterning quality, this paper will discuss along any ridge, then the ridge is removed [18]. The overlay some recent advancement of decomposition and optimization require