eda考试复习（eda考试复习）.docVIP

eda考试复习（eda考试复习） 6. in the VHDL language of the 1987 standard, the identifier describes the correct A. A. must begin with the English alphabet. B. can begin with Chinese characters. C. can begin with numbers. D. any character is OK 7. in the VHDL language of the 1987 standard, the identifier describes the correct B. A. underscores can be used with B.. Underscores cannot be used together. C. cannot use underscores. D. can use any character The description of the 15. variable and the signal is correct A. A. variable assignment number is: = B. signal assignment: = C. variable assignment number is = D. there is no difference between the two The description of the 16. variable and the signal is correct B. A. variables can take out the process, B. signals can be taken out of the process, C. signals can not bring out the process D., the two are not different 19. the following data belongs to the bit vector is D. A. 4.2, B., 3, C., 1, D., 11011 The high impedance defined in 22. STD_LOGIG_1164 is the character D. A., X, B., x, C., Z, D., Z In STD_LOGIG_1164 23., the character H defines A. A. weak signal 1 B. weak signal 0 C. without this definition D. initial value The placement of sequential statements in 32. VHDL is the correct D (used only in processes and subroutines). A. can be placed in the process statement, B. can be placed in the subroutine, C. can not be placed in any position, D. in front of the statement is correct 36. the abbreviation of programmable logic device is D. A., FPGA, B., PLA, C., PAL, D., PLD 37. the field programmable gate array is abbreviated as FPGA. A., FPGA, B., PLA, C., PAL, D., PLD 39. in EDA, the Chinese meaning of ISP is B. A. network vendor B. has no specific meaning in system programming D.; C. uses programmer to burn PLD chips 40. in EDA, the Chinese meaning of IP is D. A. network vendor B. has no specific meaning in system programming C., D. IP IP core 55. the following process is the correct FPGA / CPLD design flow based on the EDA sof