Temperature-aware microarchitecture：（Temperature-aware微体系结构）.pdfVIP

Temperature-Aware Microarchitecture †Kevin Skadron, ‡Mircea R. Stan, ‡Wei Huang, †Sivakumar Velusamy, †Karthik Sankaranarayanan, and †David Tarjan∗ †Dept. of Computer Science, ‡Dept. of Electrical and Computer Engineering University of Virginia, Charlottesville, VA {skadron,siva,karthick,dtarjan}@, {mircea,wh6p}@ Abstract power. Localized heating occurs much faster than chip-wide heat- ing; since power dissipation is spatially non-uniform across the With power density and hence cooling costs rising exponen- chip, this leads to “hot spots” and spatial gradients that can cause tially, processor packaging can no longer be designed for the worst timing errors or even physical damage. These effects evolve over case, and there is an urgent need for runtime processor-level tech- time scales of hundreds of microseconds or milliseconds. This niques that can regulate operating temperature when the pack- means that power-management techniques, in order to be used for age’s capacity is exceeded. Evaluating such techniques, however, thermal management, must directly target the spatial and temporal requires a thermal model that is practical for architectural studies. behavior of operating temperature. In fact, many low-power tech- This paper describes HotSpot, an accurate yet fast model based niques have little or no effect on operating temperature, because they do not reduce power density in hot spots, or because the