苏州大学VLSICHAP5.pptVIP

Topics Memory elements. Basics of sequential machines. Clocking disciplines Sequential machine implementation: clocking Sequential machine design. State assignment. Power optimization of sequential machines. Design validation. Sequential testing. Memory elements Stores a value as controlled by clock. May have load signal, etc. In CMOS, memory is created by: capacitance (dynamic); feedback (static). Variations in memory elements Form of required clock signal. How behavior of data input around clock affects the stored value. When the stored value is presented to the output. Whether there is ever a combinational path from input to output. Memory element terminology Latch: transparent when internal memory is being set from input. Flip-flop: not transparent—reading input and changing output are separate events. Clock terminology Clock edge: rising or falling transition. Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0). Memory element parameters Setup time: time before clock during which data input must be stable. Hold time: time after clock event for which data input must remain stable. Dynamic latch Stores charge on inverter gate capacitance: Latch characteristics Uses complementary transmission gate to ensure that storage node is always strongly driven. Latch is transparent when transmission gate is closed. Storage capacitance comes primarily from inverter gate capacitance. Latch operation ? = 0: transmission gate is off, inverter output is determined by storage node. ? = 1: transmission gate is on, inverter output follows D input. Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid. Stored charge leakage Stored charge leaks away due to reverse-bias leakage current. Stored value is good for about 1 ms. Value must be rewritten to be valid. If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid. Stick di