门电路VHDL语言资料.docVIP

“非”门 library ieee; use ieee.std_logic_1164.all; entity not1 is port(a:in std_logic; b:out std_logic); end entity not1; architecture behav of not1 is begin b=not a; end architecture behav; “与”门 library ieee; use ieee.std_logic_1164.all; entity and2 is port(a,b:in std_logic; c:out std_logic); end entity and2; architecture behav of and2 is begin c=a and b; end architecture behav; “与非”门 library ieee; use ieee.std_logic_1164.all; entity nand2 is port(a,b:in std_logic; c:out std_logic); end entity nand2; architecture behav of nand2 is begin c=not(a and b); end architecture behav; “或非”门 library ieee; use ieee.std_logic_1164.all; entity nor2 is port(a,b:in std_logic; c:out std_logic); end entity nor2; architecture one of nor2 is begin c=not(a or b); end architecture one; “异或非”门 library ieee; use ieee.std_logic_1164.all; entity xor2 is port(a,b:in std_logic; c:out std_logic); end entity xor2; architecture one of xor2 is Begin c=not( ( (not a)and b)or(a and(not b) ) ); end architecture one; D触发器 library ieee; use ieee.std_logic_1164.all; entity dffa is port(D,clk,clr:in std_logic; Q:out std_logic); end entity dffa; architecture behave of dffa is begin process(clk,D,clr) begin if clr=1 then Q=0; Elsif clkevent and clk=1 then Q=D; end if; end process; end architecture behave; T触发器 library ieee; use ieee.std_logic_1164.all; entity tffa is port(T,clk,clr: in std_logic; Q: buffer std_logic); end entity tffa; architecture behave of tffa is begin process(clk,T,clr) begin if clkevent and clk=1then if clr=1 then Q=0; Elsif t=1then Q=not Q; else Q=Q; End if; end if; end process; end architecture behave; JK触发器 library ieee; use ieee.std_logic_1164.all; entity jk is port(J,K,clk, in std_logic; Q: buffer std_logic); end entity tffa; architecture behave of jk is begin process(clk,J,K) begin if clkevent and clk=1then Q=( (J and(not Q) )or( (not K)and Q) ); end if; end pro