符号化仿真器用于CMOS模拟集成电路设计自动化的新进展-电路与系统专业论文.docxVIP

上海交通大学硕士学位论文 上海交通大学硕士学位论文 II II SYMBOLIC SIMULATOR APPLICATION ON CMOS ANALOG CIRCUIT SIZING ABSTRACT A symbolic calculation method based on the symbolic analog simulator for the sensitivity of frequency response to semiconductor device sizes is addressed for application in analog integrated circuit design in this paper. The transistor size-based ac-sensitivity can be used for sizing devices and understanding the circuit behavior. Examples are provided to demonstrate that a design platform supported by symbolic ac-sensitivity and visualization can be a helpful tool for computer aided design if analog integrated circuit. The thesis is organized as follows. A brief introduction to the history and algorithm of symbolic simulator is in Chapter 1 and Chapter 2. The algorithms and implementations of symbolic sensitivity to device sizes are presented in Chapter 3. In Chapter 4, the symbolic analog design simulator platform is introduced. Example cases and applications are demonstrated in Chapter 5. Discussions on symbolic ac-sensitivity under different working region of transistors are presented in Chapter 6. Conclusions and future work are reported in Chapter 7. The symbolic ac-sensitivity calculation in this thesis is probably the first on to reveal the connections between the sensitivity and the circuit behavior properties, such as the pole-zeros and the dc gain. It will probably help to promote the analog design methodology and automation. KEY WORDS: Analog Circuit design, AC-Sensitivity, Binary Decision Diagram (BDD), Device Sizing, Pole-Zero Analysis, Symbolic Simulation III III 目 录 第一章 绪论 ················································································································· 1 1.1 模拟集成电路设计流程和自动化 ····································································· 2 1.1.1 模拟集成电路设计流程 ·············································································· 2 1.1.2 模拟集成电路设计关键点 ····················································