Mid3 Revision Powering Silicon Valley San Jose State University中期修订为硅谷圣何塞州立大学.pptVIP

Mid3 Revision Prof. Sin-Min Lee * Step 3: Flip-Flop Transition Table * Figure 9--29 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8. Step 4: Karnaugh Maps * Figure 9--30 Karnaugh maps for present-state J and K inputs. Step 5: Logic Expressions for Flip-Flop Inputs * Figure 9--31 Three-bit Gray code counter. Step 6: Counter Implementation * Figure 9—32 : Example 9-5 * * * Figure 9--33 * Figure 9--34 * Figure 9--35 Example 9-6 - State diagram for a 3-bit up/down Gray code counter. * * * Figure 9--36 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable. * Figure 9--37 Three-bit up/down Gray code counter. * Figure 9--38 Two cascaded counters (all J and K inputs are HIGH). Cascaded Counters * Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38. * Figure 9--40 A modulus-100 counter using two cascaded decade counters. * Figure 9--41 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs. * Figure 9—42 : Example 9-7 – Determine the overall modulus * Figure 9--43 A divide-by-100 counter using two 74LS160 decade counters. * Figure 9--44 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter). * Figure 9--45 Decoding of state 6 (110). Counter Decoding * * Counters * Figure 9--1 A 2-bit asynchronous binary counter. Asynchronous Counter Operation * Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green. * * * Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. * Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. * Figure 9--5 Four-bit asynchronous binary counter and its