[工程科技]Alpha and IA64 Executive Summary.pdfVIP

Alpha and IA64 Executive Summary Applications have two types of parallelism: instruction-level parallelism and thread-level parallelism . Instruction-level parallelism enables a processor to issue multiple instructions in the same cycle. Instruction-level parallelism can be static (discovered by the compiler at compile-time) or dynamic (discovered by the processor at run-time). Thread-level parallelism enables a processor to run multiple threads, processes, or programs at the same time. An Alpha processor will exploit static and dynamic instruction-level parallelism with out- order execution, and thread-level parallelism with simultaneous multithreading. Out-of- order execution has a performance benefit of 1.5-2x over in-order execution. Simultaneous multithreading has benefit of 1.5-3x over single threaded execution. An IA64 processor will only exploit static instruction-level parallelism. It cannot take advantage of dynamic instruction-level parallelism or thread-level parallelism. IA64 defines a set of architectural extensions to permit compilers to identify more instruction- level parallelism. These architectural extensions will make it very difficult for an IA64 processor to implement out-of-order execution or simultaneous multithreading efficiently. For most applications, the small benefit that these architectural extensions give compilers does not equal the performance lost by not using these dynamic techniques. Alpha will be superior to IA64 on commercial applications . Commercial applications are very sensitive to code size. The IA64 instruction encoding increases the code size of a program by at least 33%, and the compiler techniques required by the IA64 introduce many additional instructions. Commercial programs are difficult to analyze at compile- time, and IA64 cannot dynamically adjust to program behavior at run-time. Commercial programs have very low instruction-level parallelism, but they are typically explicitly m