适合NAND闪存控制器的BCH纠错编译码器VLSI实现.PDFVIP

中国集成电路 设计 CIC China lntegrated Circult 适合NAND 闪存控制器的 BCH 纠错编译码器VLS I 实现 陈宏铭，程玉华 （北京大学上海微电子研究院上海201203） 摘要：随着大容量MP3播放器、PMP播放器、数码相机、智能手机等消费电子产品的需求持续增长，MLC的 NAND闪存已经取代SLC的NAND闪存成为市场主流。而存储容量的增大所带来良率与可靠性的下降，意 味着我们需要纠错能力更强大的硬件编译码器来处理可能发生的错误。针对固态硬盘需要支持多通道的 I/ NAND闪存，纠错编译码器也要有能够处理并行O总线的能力，本文实现了可由软件配置、最大纠错能力t 为可变的1~16b的BCH纠错编译码器，在计算错误位置多项式的过程中使用了修正的欧几里德算法。 关键词：MLC ；NAND ；BCH VLSI Implementation of BCH Codec for NAND Flash Controller CHEN Hong-ming, CHENG Yu-hua （ （ ） ） Shanghai Research Institute of Microelectronics SHRIME , Peking University, Shanghai, 201203 Abstract: Along with the increasing demand of mass storage in MP3 player, PMP player, Digital still camera, MLC NAND flash had replaced SLC NAND flash and become the main stream. The increasing storage capacity results in the decreasing of yield and reliability. It means that we need a powerful error correction hardwire codec to handle the possibility of error happened. The Error correction codec for multi-channel solid state disk need the capability to do parallel processing for parallel I/O. In this paper, we implemented the BCH codec with the error correction capability t vary from 1 to 16b which can be configurable by software. A modified version of the Euclidean Algorithms that is specifically adapted to the RS decoding error location. Keywords: MLC; NAND; BCH 1 引言 来越近，漏电明显，甚至采用单位记忆储存单元的多 位化（Multi- Bit per Cell）的结构导致的良率与可靠 NAND 闪存在工厂制作过程存在缺陷产生的可 性的下降，或者是对其进行