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simtile片状多核处理器的高效模拟器 simtile an efficient simulator of tiled chip multi-processor
ISSN 1673-9418 CODEN JKYTA8 E-mail: fcst@
Journal of Frontiers of Computer Science and Technology
1673-9418/2010/04(12)-1115-06 Tel: +86-10
DOI: 10.3778/j.issn.1673-9418.2010.12.006
*
SimTile: An Efficient Simulator of Tiled Chip Multi-processor
+
LIU Tao , JI Zhenzhou, WANG Qing
School of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001, China
+ Corresponding author: E-mail: liutao07@
SimTile:*
+
, ,
, 150001
Tiled CMP(chip multi-
processor),
, Tiled
16 , SimTile ,
, ,
cache ,
,
片状多核处理器;模拟器;互联结构;数据一致性
A TP309
LIU Tao, JI Zhenzhou, WANG Qing. SimTile: An efficient simulator of tiled chip multi-processor. Journal of
Frontiers of Computer Science and Technology, 2010, 4(12): 1115-1120.
Abstract: Traditional bus sharing multi-processor chips meet bottleneck trouble with the number of processor cores
increasing. In the structure design of novel Tiled CMP(chip multi-processor), onchip interconnection shows great
impact on platform scalability and performance. Implementation of low latency and high bandwidth onchip routing
structure becomes current hotspot. Execute-driven SimTile is implemented by a structure of Tiled 16-core CMP de-
*The National Natural Science Foundation of China under Grant No().
Received 2010-05, Accepte
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