前瞻加法器（CLA）设计之数位乘法器.PDFVIP

前瞻加法器 (CLA)設計之數位乘法器 A CMOS Digital Multiplier Design Using Carry Look-Ahead Adders 李嘉龍(Chia-Lung Lee) 、劉偉行*(Weihsing Liu) 國立虎尾科技大學 電子工程系 摘要 本論文係利用前瞻式加法器實現44 數位乘法器。相較於傳統加法器實現之 44 乘法器 ，本電路具有減少延遲時間的優點。由於在算術的四則運算中以加減 法使用頻率最高，因此加法器的運算速度會影響到整個系統的執行速度。傳統的 加法器進位延遲會隨著輸入字組長度成正比增加，所以若以傳統加法器設計乘法 器，延遲時間的累積將會非常可觀 。本論文以前瞻加法器設計44 乘法器，將每 一級之進位以平行的方法處理，有效減少了延遲時間。本電路經由HSPICE 電路 模擬軟體的模擬 ，在使用0.35 微米N-Well 2P4M 的製程參數下 ，電路操作頻率 可達到100MHz 。而在3.3V 的供應電壓下, 瞬間最大功率消耗為3.37m W 。 關鍵字 ：前瞻加法器 、進位延遲 、乘法器 。 Abstract A carry look-ahead adders based 44 digital multiplier has been proposed in thispaper. Comparing with the traditional adder based design, the proposed circuit benefits from its shorter propagation time. Since the adding or subtracting is the most frequently used operation of the basic arithmetic operations. Therefore, the operating time of the adder will seriously affect the processing time of the entire system. However, the carry-delay time of the traditional adder is proportional to the length of the input word, which will result in a very serious delay problem. Consequently, the carry look-ahead adder, which uses the parallel processing approach to handle the carry operation, is used in the proposed digital multiplier, and it effectively reduces the operating time. The proposed multiplier has been simulated by the HSPICE emulation program, where an N-Well 2P4M process was used. The simulation results show that the proposed circuit can operate at the signal frequency up to 100MHz. Also, with the supply voltage of 3.3V, the instantaneous maximum power dissipation is 3.37mW. Keywords: carry look-ahead adder, propagation delay, multiplier. 壹 、簡介 數位乘法器是一種廣泛使用於數位系統中的電路[1-5] ，例如，cpu