spi-spec详解.docVIP

Serial Peripheral Interface Bus SPI?总线是Motorola公司推出的三线同步接口，同步串行3线方式进行通信:一条时钟线SCK，一条数据输入线MOSI，一条数据输出线MISO;用于CPU与各种外围器件进行全双工、同步串行通讯。SPI主要特点有:可以同时发出和接收串行数据;可以当作主机或从机工作;提供频率可编程时钟;发送结束中断标志;写冲突保护;总线竞争保护等。During each SPI clock cycle, a full duplex data transmission occurs: （主要是在sck的控制下，两个双向移位寄存器进行数据交换。the master sends a bit on the MOSI line; the slave reads it from that same line the slave sends a bit on the MISO line; the master reads it from that same line 2、时钟极性及相位： In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescales SPI Block Guide [1] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention. The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device. At CPOL=0 the base value of the clock is zero For CPHA=0, data is captured on the clocks rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition). For CPHA=1, data is captured on the clocks falling edge and data is propagated on a rising edge. At CPOL=1 the base value of the clock is one (inversion of CPOL=0) For CPHA=0, data is captured on clocks falling edge and data is propagated on a rising edge. For CPHA=1, data is captured on clocks rising edge and data is propagated on a falling edge. 3、以MX29L12845E为例： read bytes 主机把一位数据放到(主出从进)上，其实就是把相应的线拉高(1)或者拉低(0)；然后主机让S(时钟)上升一次，数据将在S的上升沿被slave接受；主机再把时钟拉低，以备下次将其拉高；这样重复8次，就可以把一个byte的指令送到slave了。第一次传指令，第二次就是传要读的地址；传完指令和地址，主机就可以一次次把时钟拉高，一位一位地读取到slave传来的数据了。 Timing analysis 伪代码： set_line(SPI_S, low); //选中，表示要开始交互 set_line(SPI_C, low); //clock拉低，以保证待会可以“拉高” for(i＝0；i 8; i++) { //传指令 set_line(SPI_D, BIT(command, i)); set_line(SPI_C, high); ------| set_line(SPI_C, low);--------| } for(i＝0；i ; i++) { //传地址 set_line(SPI_D, BIT(addr, i)); set_line(SPI_C, high); set_line(SPI_C, low); } for(i＝0；i 8; i++) { //