SPI完整程序.docxVIP

SPI接口源程序modulesimple_spi_top( // 8bit WISHBONE bus slave interfaceinput wireclk_i, // clockinput wirerst_i, // reset (asynchronous active low)input wirecyc_i, // cycleinput wirestb_i, // strobeinput wire [1:0] adr_i, // addressinput wirewe_i, // write enableinput wire [7:0] dat_i, // data inputoutputreg [7:0] dat_o, // data outputoutputregack_o, // normal bus terminationoutputreginta_o, // interrupt output // SPI portoutputregsck_o, // serial clock outputoutput wire mosi_o, // MasterOutSlaveINinput wiremiso_i // MasterInSlaveOut); // // Module body //reg [7:0] spcr; // Serial Peripheral Control Register (HC11 naming)wire [7:0] spsr; // Serial Peripheral Status register (HC11 naming)reg [7:0] sper; // Serial Peripheral Extension registerreg [7:0] treg, rreg; // Transmit/Receive register // fifo signalswire [7:0] rfdout;regwfre, rfwe; wire rfre,rffull,rfempty;wire [7:0]wfdout;wirewfwe, wffull, wfempty; // misc signalswiretirq; // transfer interrupt (selected number of transfers done)wirewfov; // write fifo overrun (writing while fifo full)reg [1:0] state; // statemachine statereg [2:0] bcnt; // // Wishbone interfacewirewb_acc = cyc_i stb_i; // WISHBONE accesswirewb_wr = wb_acc we_i; // WISHBONE write access // dat_ialways @(posedgeclk_i or negedgerst_i)if (~rst_i)beginspcr = #1 8h10; // set master bitsper = #1 8h00;endelse if (wb_wr)beginif (adr_i == 2b00)spcr = #1 dat_i | 8h10; // always set master bitif (adr_i == 2b11)sper = #1 dat_i;end // write fifoassignwfwe = wb_acc (adr_i == 2b10) ack_o we_i;assignwfov = wfwe wffull; // dat_oalways @(posedgeclk_i)case(adr_i) // synopsysfull_caseparallel_case 2b00: dat_o = #1 spcr; 2b01: dat_o = #1 spsr; 2b10: dat_o = #1 rfdout; 2b11: dat_o = #1 sper;endcase // read fifoassignrfre = wb_acc (adr_i == 2b10) ack_o ~we_i;