1_1_C6000体系结构和汇编语言.pptVIP

C6000 体系结构和汇编语言;Why DSP?;Describe C6000 CPU architecture. Introduce instructions by an example.Three type instructions;General DSP System Block Diagram;C6000 CPU Architecture;对比：TigerShare101 Architecture;C6201/04/05 片内存储器;C6701片内存储器;C64x 片内2级存储器;程序员角度的DSP结构：存储器的层次;C62xx CPU Core;C67xx CPU Core;C64xx CPU Core;一条C6000的指令和其机器码;对比：8086的ADD指令; Implementation of Sum of Products (SOP) ; Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required;Multiply (MPY);Multiply (.M unit);Addition (.?);Add (.L unit);Register File - A;Specifying Register Names;Specifying Register Names;Data loading;Load Unit “.D”;Load Unit “.D”;Load Instruction;Load Instructions (LDB, LDH,LDW,LDDW);Using the Load Instructions;The syntax for the load instruction is: Where: Rn is a register that contains the address of the operand to be loaded and Rm is the destination register. ;The syntax for the load instruction is: The question now is how many bytes are going to be loaded into the destination register? ;The syntax for the load instruction is: ;Using the Load Instructions;Using the Load Instructions;The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL .? a, A5 (‘a’ is a constant or label) How many bits represent a full address? 32 bits So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode). ;To solve this problem another instruction is available: MVKH ;Loading the Pointer Rn;LDH, MVKL and MVKH;Creating a loop;Creating a loop;What are the steps for creating a loop;1. Create a label to branch to; MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loop LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop ;Which unit is used by the B instru