数字电路7.3.pptVIP

制作：金燕华 7.3 Clocked Synchronous State-Machine Analysis （时钟同步状态机分析） 7.3 Clocked Synchronous State-Machine Analysis （时钟同步状态机分析） 7.3 Clocked Synchronous State-Machine Analysis （时钟同步状态机分析） 7.3 Clocked Synchronous State-Machine Analysis （时钟同步状态机分析） State-Machine Structure State-Machine Structure State-Machine Analysis Basic steps: Determine excitation equation F and output equation G; Substitute excitation equation F into the characteristic equation of the flip-flop to get the next-state Q*; Use Q* and G to construct a state/output table; (Optional) Draw a state diagram, timing diagram, etc. Example 1: State machine using D Flip-Flops state（状态） The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behavior. 时序电路的状态是一个状态变量的集合，这些状态变量在任意时刻的值都包含了为确定电路未来状态而必须考虑的所有历史信息。 Several definitions state-machine（状态机） A state-machine usually refers in particular to a sequential circuit composed by flip-flot(s), and the state transition is controlled by a clock signal. 通常特指用触发器构成的时序电路，用时钟信号来控制状态的转换。 Several definitions clocked synchronous state-machine All of the flip-flops use the same clock signal, and the state-machine changes state only when the triggering edge occurs on the clock signal. 构成“状态机”的所有触发器都使用同一个时钟输入，这种状态机只在时钟信号的触发沿才改变其状态。 Several definitions Several definitions CLK tper tH tL period: tper frequency: 1/tper duty cycle：tH/tper、tL/tper clock period, clock frequency, duty cycle (时钟周期、时钟频率、占空比) Fig. 7-1 Combinational Logic Three parts: State Memory next state = H(current state, excitation) Next-state Logic excitation = F(current state, input) Output Logic output = G(current state, input) transition equation excitation equation output equation Mealy machine: The output depends on both state and input. Moore machine: The output depends only on the state. Two models: (depending on the output logic) Mealy