AN712AlteraJESD204BMegaCoreFunctionandADIAD分析.PDFVIP

Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report 2016.06.13 AN-712 Subscribe Send Feedback ® The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices. This report highlights the interoperability of the JESD204B IP core with the AD9625 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results. Related Information • JESD204B IP Core User Guide • ADI AD9625 Datasheet Hardware Requirements The hardware checkout test requires the following hardware and software tools: • Stratix V Advanced Systems Development Kit with 15 V power adaptor • Arria 10 GX FPGA Development Kit • ADI AD9625 EVM • Mini-USB cable • Clock source card capable of generating device clock frequencies Hardware Setup for Stratix V Advanced Systems Development Kit A Stratix V Advanced Systems Development Kit is used with the ADI AD9625 daughter card module attached to the FMC connector of the development board. • The AD9625 EVM derives power through the development kit FMC connector. • The ADC device clock is supplied by external clock source card through the SMA connector on the AD9625 EVM. • The AD9625 divides the sampling clock by four and supplies this divided cl