门路延迟(国外英文资料).docVIP

路径延迟(国外英文资料) One way to check the sequence of time is sequence simulation, which calculates the delay value associated with the module in the simulation process; The second is static sequential validation. (1) delay type Distribution delay: on the basis of each individual element to define a way of modeling is to delay value is assigned to separate door, the other is a delay value specified in the separate the assign statement. The total delay: defined on the basis of each individual module, the surface appears to be the delay of the module output gate. It is easier to model than a distribution delay. The delay of the foot to the foot (the path) : the delay in assigning the delay to all the paths from each input to each output in the module. Therefore, the delay can be specified for each input/output path. For large circuits, it is easier to model than a distribution delay, and the designer only needs to understand the input and output of the module, without knowing the inside of the module. (2) path delay Specify pieces: Module path delay: the delay between the source of the module and the target. The path delay is assigned between the keyword specify and endspecify. The block contains a sequence of timing delays for all the paths that pass through the module, setting up a sequence check in the circuit, and defining the specparam constant. Ex. : Module M (out, a, b, c, d); The output out; Input a, b, c, d; Wire e, f; specify (a = out) = 9; (b = out) = 9; (c = out) = 11; (d = out) = 11; endspecify And a1 (e, a, b); And a2 (f, c, d); And a3 (out, e, f); endmodule The specify block is an independent part of the block that is not present in any other module, such as initial or always, and the internal statement must be very specific. Specify piece inside: Parallel connection: each path statement has a source domain and a target domain, each corresponding is linked together, if is a vector must be the same digits, such as case (source = destination) = delay_value