LOW OVERHEAD DELAY TESTING OF ASICS.pdfVIP

LOW OVERHEAD DELAY TESTING OF ASICS Pamela Gillis, Kevin McCauley*, Francis Woytowich, and Andrew Ferko IBM Corporation Essex Junction, VT 05465 USA *Cadence Design Systems Endicott, NY 13760 USA Abstract Delay testing has become increasingly essential as chip geometries shrink [1,2,3]. Low overhead or cost effective delay test methodology is successful when it results in a minimal number of effective tests and eases the demands on an already burdened IC design and test staff. This paper describes one successful method in use by IBM ASICs that resulted in a slight total test pattern increase, generally ranging between 10 and 90%. Example ICs showed a pattern increase of as little as 14% from the stuck-at fault baseline with a transition fault coverage of 89%. In an ASIC business, a large number of ICs are processed, which does not allow for the personnel to understand how to test each individual IC design in detail. Instead, design automation software that is timing and testability aware ensures effective and efficient tests. The resultant tests detect random spot timing delay defects. These types of defects are time zero related failures and not reliability wearout mechanisms. . 1. Introduction Some random spot defects that slow the transition of a signal were relatively benign in slower technologies with larger device and wiring features, but are delay defects which impact the circuit function in .18 micron and smaller technologies. Early studies on CMOS ASIC products and the initial attempts at delay test techniques within IBM in the late 1980’s did show defect reduction benefits [4]. This work guided CMOS metal wiring and other process improvements, continuous quality monitoring actions, and delay test methodology development. Integrated circuit (IC) defects include wire and interconnect via opens (complete and resistive), bridging between wires, and parametric defects [5,6]. As the device sizes