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Elevated SourceDrain Engineering by Novel Technology for FullyDepleted SOI CMOS Devices and.pdf

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Elevated SourceDrain Engineering by Novel Technology for FullyDepleted SOI CMOS Devices and

第 26 卷　第 4 期 2005 年 4 月　　半　导　体　学　报 CHIN ESE J OURNAL OF SEMICONDUCTORS Vol. 26 　No. 4 　　Apr. ,2005 Lian J un 　male ,was born in 1976 ,PhD candidate. His main research field is fully2depleted SOI CMOS devices and circuit s. Email :junlian @ hot mail . com Hai Chaohe 　male ,was born in 1942 ,professor . His main research fields are SOI SRAM ,radiation hardening process technologies ,and Bi2 CMOS devices and circuit s. Received 3 J une 2004 ,revised manuscript received 2 December 2004 Ζ 2005 Chinese Institute of Elect ronics Elevated Source/ Drain Engineering by Novel Technology for Fully2Depleted SOI CMOS Devices and Circuits Lian J un and Hai Chaohe ( I nsti t ute of Microelect ronics , Chinese A cadem y of Sciences , Bei j ing 　100029 , China) Abstract : 0135μm thin2film fully2depleted SOI CMOS devices with elevated source/ drain st ructure are fabricated by a novel technology. Key process technologies are demonst rated. The devices have quasi2ideal subthreshold properties ; the subthreshold slope of nMOSFETs is 65mV/ decade ,while that of pMOSFETs is 69mV/ decade. The saturation current of 112μm nMOSFETs is increased by 32 % with elevated source/ drain structure ,and that of 112μm pMOS2 FETs is increased by 24 %. The per2stage propagation delay of 1012stage fully2depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage. Key words : FDSOI ; CMOS ; elevated source/ drain EEACC : 2560 CLC number : TN386 　　　Document code : A 　　　Article ID : 025324177 (2005) 0420672205 1 　Introduction As CMOS technology continues to scale down ,f ully2depleted SOI ( FDSO I) technology as2 sumes a prominent position as a potential solution to the problems associated wit h continued device scaling [ 1 ] . Some of the benefit s of using FDSO I are reduction of junction capacitance ,immunity for ra2 diation ,latch up2f ree for complementary metal2ox2 ide2semiconductor ( CMOS) [2 ] , suppression of the short2channel effect s[3 ] ,p rocess simplicity[4 ] , high2 er device packi