EDAII实验报告—多功能数字钟2_南京理工大学.doc

EDAII实验报告—多功能数字钟2_南京理工大学.doc

  1. 1、有哪些信誉好的足球投注网站(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
  2. 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  3. 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
EDAII实验报告—多功能数字钟2_南京理工大学.doc

EDA设计Ⅱ实验报告 ——多功能数字钟设计 姓名: 学号* 指导老师:姜萍 完成时间:2013年12月 目录 一、实验内容实验SmartSOPC试验系统中,验证电路的设计是否正确。 关键词:数字钟,FPGA ,QuartusII,SmartSOPC,分模块设计 Summary: Digital clock has been an necessary part of our daily life.The content of this essay is the design of multi-function digital clock, which has the functions of 24-hour timer,time adjustment, time cleared, the time to maintain, the whole point timekeeping and alarm. First,the content and demands of experiment is presented in the essay,the design principle of multi-function digital clock is also introduced.The method of module integration after designing and simulating each module is taken to implement the experiment.After packaging all module,all the modules are integrated to realize the final electric circuits,implementing all the demands of multi-function digital clock design. Second,the method and steps of the experiment is presented.Using programmable logic devices,the electric circuits are designed in software QuartusII to realize the multi-function,which is called FPGA. Firstly, the frequency dividing circuit is designed to get the frequency required by dividing the frequency of 48MHZ from the experiment box.Then,the timing circuit and decoding-and-display circuit are also designed,which are all simulated in software to test their validity.After all,the time adjustment circuit,the time maintain circuit,the time cleared circuit and the alarm circuit are also designed,which are simulated in the software to test their correctness.After packaging all the circuits into modules,the modules are integrated to finish the multi-function digital clock design. Last,the final circuit is downloaded to the SmartSOPC experiment system to test its validity after assigning all the pins of the final circuits. Keywords:digital clock, FPGA ,QuartusII,SmartSOPC,points module design 一、实验内容 题目简介:设计一个数字计时器,可以完成00:00:00到23:59:59的计

文档评论(0)

基本资料 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档