第九周 数字分频器、乘法器、序列检测器.ppt

任务一：分频电路的设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk_div IS PORT(clk :IN STD_LOGIC; clk_div2 :OUT STD_LOGIC; clk_div4 :OUT STD_LOGIC; clk_div8 :OUT STD_LOGIC; clk_div16 :OUT STD_LOGIC); END clk_div; ARCHITECTURE rtl OF clk_div6 IS SIGNAL count :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk) BEGIN IF (clk’EVENT AND clk =’1’) THEN IF (count = “1111”) THEN count = (OTHERS=’0’); ELSE count = count+1 ; END IF; END IF; END PROCESS; Clk_div2 = count(0); Clk_div4 = count(1); Clk_div8 = count(2); Clk_div16 = count(3); END rtl; 6分频的分频电路 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk_div6 IS PORT(clk :IN STD_LOGIC; clk_out :OUT STD_LOGIC); END clk_div6; ARCHITECTURE rtl OF clk_div6 IS SIGNAL clk_temp :STD_LOGIC; BEGIN PROCESS(clk) VARIABLE counter: INTEGER RANGE 0 TO 15; CONSTANT md: INTEGER :=3; BEGIN IF (clk’EVENT AND clk =’1’) THEN IF (counter = md) THEN Counter := 0; Clk_temp = NOT clk_temp; ELSE Counter := counter +1 ; END IF; END IF; END PROCESS; Clk_out = clk_temp; END rtl; ？若需要得到的占空比不是1：1的分频电路，应如何设计分频电路？ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk_div16 IS PORT(clk :IN STD_LOGIC; clk_out :OUT STD_LOGIC); END clk_div16; ARCHITECTURE rtl OF clk_div16 IS SIGNAL counter :STD_LOGIC; BEGIN 16分频电路，分频后时钟信号的占空比为1：15 P1: PROCESS(clk) BEGIN IF (clk’EVENT AND clk =’1’) THEN IF (counter =”1111”) THEN Counter = (OTHERS=’0’); ELSE Counter := counter +1 ; END IF; END IF; END PROCESS; P2: PROCESS(clk) BEGIN