片上互连建模及其特性分析.docVIP

  Modeling and Characterization of On-Chip Interconnects# YIN Wenyan, ZHAO Wensheng* 5 10 15 (Centre for optical and electromagnetic research, MOI, Zhejiang university, Hangzhou, 310058, China) Abstract: In this article, one distributed circuit model for the on-chip single interconnect will be introduced at first, where all the lumped elements are frequency-independent and can be directly obtained from its geometrical and physical parameters. This ensures proper scalability of the model parameters because no optimization tuning or fitting for them is involved. Some popular and low-cost techniques, such as patterned ground shield (PGS) structures for suppressing the substrate loss of silicon substrate at high frequencies and differential signal transmission are also addressed here. Then, electromagnetic modeling of on-chip coupled (a)symmetrical interconnects will be performed, including all distributed parameters. The average power handling capability (APHC) of on-chip interconnects and even thin-film microstrip lines (TFML) are also addressed here. Finally, the electrothermal analysis of multilevel interconnects under electrostatic discharge (ESD) stress will be reported using the time-domain FEM. Key words: Microwave technique, Interconnect; distributed parameter; average power handling capability; time-domain finite element method (TD-FEM); electrothermal response. 20 0 Introduction Silicon technology has entered the realm of millimeter-wave frequencies and a lot of silicon-based systems have been reported which operate at so high frequencies [1, 2]. In these applications, on-chip interconnects have been widely used for building up various circuits [3, 4], and therefore, scalable and wideband circuit models for the interconnects with different geometries are very important for the 25 30 35 development of silicon-based radio-frequency integrated circuits (RF IC) with good performance. In order to accurately model on-chip interconnects, we must thoroughly u