THC63LVD103D THine LVDS芯片规格书.pdfVIP

THC63LVD103D _Rev.2.1_E THC63LVD103D THine 代理商 深圳海默科技有限公司 135MHz 30Bits COLOR LVDS Transmitter 地址：深圳市福田区竹子林益华大厦 General Description Features The THC63LVD103D transmitter is designed to sup- • Wide dot clock range: 8-135MHz suited for NTSC, port pixel data transmission between Host and Flat VGA, SVGA, XGA,SXGA and SXGA+ Panel Display from NTSC up to SXGA+ resolutions. • PLL requires no external components The THC63LVD103D converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) • Supports spread spectrum clock generator data stream. The transmitter can be programmed for ris- • On chip jitter filtering ing edge or falling edge clocks through a dedicated pin. • Clock edge selectable At a transmit clock frequency of 135MHz, 30bits of • Supports reduced swing LVDS for low EMI RGB data and 5bits of timing and control data • Power down mode (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit- ted at an effective rate of 945Mbps per LVDS channel. • Low power single 3.3V CMOS design • 64pin TQFP • Pin compatible with THC63LVD103(30bits)t Block Diagram CMOS/TTL INPUT LVDS OUTPUT