NS ADC16V130低IF接收器参考设计.docxVIP

NS ADC 16V130低IF接收器参考设计 NS公司的ADC 16V130是LVDS输出的16位130MSPS高性能ADC,双电源1. 8V和 3. 0V工作，16位分辨率,取样速率130MSPS,满功率带宽1. 4GHz, 160-MHz的SNR 为76. 7dB, SFDR为90. 6dBFS,主要应用在高IF取样接收器，多载波基站接收器, 测试测量设备,通信基础设备,数据采集和手提仪表等.本文介绍了 ADC16V130主 要特性,方框图，低频和高频变压器驱动电路以及SP16130CH4RB低IF接收器参 考设计主要特性,详细电路图和材料清单(BOM). ADC16V130: 16-Bit, 130 MSPS A/D Converter with LVDS Outputs converter uses a differential, error correction and an onchip power consumption and external excellent dynamic performance.The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This pipelined architecture with digital samp1e-and-ho1d circuit to minimize component count while providing converter uses a differential, error correction and an onchip power consumption and external excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique samp1e-and-ho1d stage yields a fullpower bandwidth of 1. 4 GHz. The digital data is provided via full data rate LVDS outputs - making possible the 64-pin, 9mm x 9mm LLP package. The ADC16V130 operates on dual power supplies +1.8V and +3. 0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation. ADC16Vl30主要特性: ■ Dual Supplies: 1. 8V and 3. 0V operation ■ On chip automatic calibration during power-up ■ Low power consumption ■ Multi-level multi-function pins for CLK/DF and PD ■ Power-down and sleep modes ■ On chip precision reference and samp