Prime Time PT入门培训教学PPT课件.ppt

set_multicycle_path 2 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D] Unconstrained paths SYS_CLK SDRAM_CLK 缺省的条件下，PT不会产生无约束路径的时序报告 Set timing_report_unconstrained_paths true Report_timing –from [get_clocks SYS_CLK] \ -to [get_clocks SDRAM_CLK] Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_rst_n_buf_reg (rising edge-triggered flip-flop clocked by SYS_CLK) Endpoint: I_ORCA_TOP/I_SDRAM_WRITE_FIFO/empty_int_reg (recovery check against rising-edge clock SDRAM_CLK) Path Group: (none) Path Type: max Point Incr Path I_ORCA_TOP/I_RESET_BLOCK/sys_rst_n_buf_reg/CP (sdcrq1) 0.0000 0.0000 r I_ORCA_TOP/I_RESET_BLOCK/sys_rst_n_buf_reg/Q (sdcrq1) 0.3175 0.3175 f I_ORCA_TOP/I_RESET_BLOCK/U93/Z (aor21d1) 0.2920 0.6095 f I_ORCA_TOP/I_RESET_BLOCK/sys_rst_n (RESET_BLOCK) 0.0000 0.6095 f I_ORCA_TOP/I_SDRAM_WRITE_FIFO/fifo_rst_n (SDRAM_WFIFO) 0.0000 0.6095 f I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U93ASThfnInst566/Z (bufbda) 0.2178 0.8272 f I_ORCA_TOP/I_SDRAM_WRITE_FIFO/U93ASThfnInst568/Z (bufbd1) 0.4811 1.3083 f I_ORCA_TOP/I_SDRAM_WRITE_FIFO/empty_int_reg/CDN (sdcrb1) 0.1576 1.4658 f data arrival time 1.4658 (Path is unconstrained) No paths VS no constrained paths SYS_CLK SDRAM_CLK Report_timing –from FF1/clk –to FF3/D No constrained paths. Set timing_report_unconstrained_paths true Report_timing –from FF1/clk –to FF3/D No paths. 时序解决方法 report_bottleneck –cost_type fanout_endpoint_cost Cell Reference Bottleneck cost U1/FF1 Q 100.00 get_alternative_lib_cell –lib my_lib FF1 {“fdef1a5”, “fdef1a30”} This cell is Involved in 100 violations 时序分析常用命令 Report_analysis_coverage Type of Check Total Met Violated Untested setup 6724 5366 ( 80%) 0 ( 0%) 1358 ( 20%) hold 6732