低噪声电荷泵锁相环分析与设计-集成电路工程专业论文.docxVIP

华 华 中 科 技 大 学 硕 士 学 位 论 文 II II Abstract The charge-pump PLL is a kind of circuit which is widely applied , it is the basis of clock data recovery circuit . Now, with the increase of integration level and lower voltage, a higher request to charge-pump phase-locked loop about the noise performance has been put forward. Low-noise design gradually becomes a difficulty and new frontiers. In order to reduce the output noise of PLL, we mainly work in three aspects: first of all, we improve the traditional circuit from the circuit structure, such as design low-noise vco、 no-dead zone PFD,low-spur charge pump etc; then, in order to reduce noise of the charge-pump phase-locked loop, we can start from optimization for loop bandwidth, the noise performance of charge-pump phase-locked loop is showed different according to different bandwidth;finally, excellent layout design can also reduce noise of the charge-pump phase-locked loop. This thesis studies the linear model of second order charge-pump phase-locked loop ,based on it, the stability of the loop is analyzed and a noise model is made to every function module of charge-pump phase-locked loop . It provides theory basis for designing low-noise from structure and loop parameter. In circuit structure , according to requirement of low-noise phase-locked loop, the selection about structure of vco and the number of stages, and the influence that the linearity of the load of each level’s difference pair bring to system have been discussed. According to noise theory of the vco , I design low-noise VCO and further improve noise performance; also according to the requirement of eliminating dead zone,I design high-performance PFD; according to the requirement of eliminating non-ideal effects, I design low-spur charge pump. Finally, I make the noise performance of charge pump phase-locked loop get further improvement through optimizing the loop bandwidth. This paper adopts SMIC 0.25 μm  process , new structure that it’