Testing in the Fourth Dimension Samul Ginn College of 在第四维度测试吉恩塞缪尔学院.pptVIP

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Testing in the Fourth Dimension Samul Ginn College of 在第四维度测试吉恩塞缪尔学院.ppt

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Testing in the Fourth Dimension Samul Ginn College of 在第四维度测试吉恩塞缪尔学院

Lecture 10: DFT and Scan Lecture 10: DFT and Scan Copyright 2001, Agrawal Bushnell Lecture 10: DFT and Scan * VLSI Testing Lecture 10: DFT and Scan Definitions Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Boundary scan Summary Copyright 2001, Agrawal Bushnell Lecture 10: DFT and Scan * Definitions Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus Copyright 2001, Agrawal Bushnell Lecture 10: DFT and Scan * Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Copyright 2001, Agrawal Bushnell Lecture 10: DFT and Scan * Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Copyright 2001, Agrawal Bushnell Lecture 10: DFT and Scan * Scan Design Rules Use o