vhdl语言数字钟代码.docVIP

顶层文件 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock is PORT(CP : IN STD_LOGIC; CR : IN STD_LOGIC; AK1 : IN STD_LOGIC; AK2 : IN STD_LOGIC; Q1: out STD_LOGIC_VECTOR(3 DOWNTO 0); Q2: out STD_LOGIC_VECTOR(3 DOWNTO 0); Q3: out STD_LOGIC_VECTOR(3 DOWNTO 0); Q4: out STD_LOGIC_VECTOR(3 DOWNTO 0); Q5: out STD_LOGIC_VECTOR(3 DOWNTO 0); Q6: out STD_LOGIC_VECTOR(1 DOWNTO 0)); end; architecture one of clock is COMPONENT count60_v PORT(cp : IN STD_LOGIC; cr : IN STD_LOGIC; qa: out STD_LOGIC_VECTOR(3 DOWNTO 0); qb: out STD_LOGIC_VECTOR(3 DOWNTO 0); co: OUT STD_LOGIC); END COMPONENT; COMPONENT count24_v PORT(cp : IN STD_LOGIC; cr : IN STD_LOGIC; qa: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); qb: OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); END COMPONENT; COMPONENT count100000_v PORT(cp : IN STD_LOGIC; co: OUT STD_LOGIC); END COMPONENT; COMPONENT or2_v PORT(a : IN STD_LOGIC; b : IN STD_LOGIC; y : OUT STD_LOGIC); END COMPONENT; SIGNAL tmp1,tmp2,tmp3,tmp4,tmp5 : STD_LOGIC; FOR U1 : count100000_v USE ENTITY work.count100000_v( count100000_arc); FOR U2,U3 : count60_v USE ENTITY work.count60_v( count60_arc); FOR U4 : count24_v USE ENTITY work.count24_v( count24_arc); FOR U5,U6 : or2_v USE ENTITY work.or2_v( or2_arc); begin U1 : count100000_v PORT MAP(cp=CP,co=tmp1); U2 : count60_v PORT MAP(cp=tmp1,cr=CR,qa=Q1,qb=Q2,co=tmp2); U5 : or2_v PORT MAP(a=tmp2,b=AK1,y=tmp3); U3 : count60_v PORT MAP(cp=tmp3,cr=CR,qa=Q3,qb=Q4,co=tmp4); U6 : or2_v PORT