VHDL的基本描述语句（第六七八九十一二讲）.pptVIP

case 表达式的注意点 所有分支都要覆盖且不重叠 选择项是静态值 Others用于最后，且唯一 十一、 文本文件操作（TEXTIO） 十五、 决断函数 决断函数定义了当一个信号有多个驱动源时以什么样的方式将这些驱动源的值决断为一个单一的值。 顺序语句和并发语句 3.8 VHDL描述风格 行为描述 数据流（寄存器传输）描述 结构描述 VHDL Design Styles Entity (XOR3 Gate) entity XOR3 is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; RESULT : out STD_LOGIC ); end XOR3; Dataflow Architecture (XOR3 Gate) Dataflow Description Describes how data moves through the system and the various processing steps. Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter. Data Flow is most useful style when series of Boolean equations can represent a logic. Structural Architecture (XOR3 Gate) architecture XOR3_STRUCTURAL of XOR3 is signal U1_OUT:STD_LOGIC; component XOR2 is port( I1 : in STD_LOGIC; I2 : in STD_LOGIC; Y : out STD_LOGIC ); end component; begin U1: XOR2 port map (I1 = A, I2 = B, Y = U1_OUT); U2: XOR2 port map (I1 = U1_OUT, I2 = C, Y = RESULT); end XOR3_STRUCTURAL; Component and Instantiation (1) Named association connectivity (recommended) Component and Instantiation (2) Positional association connectivity (not recommended) Structural Description Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks. Behavioral Architecture (XOR Gate) architecture XOR3_BEHAVIORAL of XOR3 is begin XOR3_BEHAVE: process (A,B,C) begin if ((A xor B xor C) = 1) then RESULT = 1; else RESULT = 0; end if; end process XOR3_BEHAVE; end XOR3_BEHAVIORAL; Behavioral Description It