eda_dsp教学第一章_概述.ppt

Product Roadmap Limited Markets for ASSPs ASICs ASIC/ASSP Development Cost $30M Simple ROI Model 20% RD of Revenue 10% Market Share $150 Million Revenue Market of $1.5 Billion Very Few Markets Large Enough!! PLD FPGA Market Forecast $B Additional Market Forecast $B Cyclone II Second-Generation 90nm FPGA Family Replacement for ASIC/ASSP 3X Cyclone Density 25% Lower Logic Cost Completed Plan Phase Q4 Cyclone II Overview Cyclone Vs. Spartan-3 Low-Cost Microprocessor A Controller For All Markets The Best Things in Life Are Free Entire Cyclone Family Supported Today Download Quartus II Web Edition Software at No Cost Cyclone-Optimized Intellectual Property (IP) Cores Available Today Includes: 10/100 Ethernet MAC SOPC Builder Memory Controllers Cyclone-Optimized IPAvailability Example Application:Digital Set-Top Box Example Application:Digital Set-Top Box Altera’s Low-Cost Roadmap Device Availability The “Perfect Storm” Industry’s First Truly Cost-Optimized Solution Half the Cost, 3X More Density than Competing Devices Low-Cost Configuration Devices “Tailored” Feature Set Designed to Requirements of High-Volume Applications Active Engagements Underway Customers Designing with Software Since July 2002 Volume Production in Q2 ‘03 Cyclone Device Floorplan FPGA Competition Need for Two Technologies Reduction, Not Optimization Logic Memory Comparison Competing at the Low End Feature Comparison Competitive Misrepresentation ASIC Competition The Value Proposition of Programmability Increasing Mask Wafer Costs Increasing Mask Layers Finer GeometryProcesses New Equipment Increasing Development Costs Increasing Mask Wafer Costs for allSemiconductorDesign Starts Longer Design Time Longer PR Time Longer Verification Time FPGA vs. ASIC: Historical Volume Crossover Point FPGA vs. ASIC: Cyclone Volume Crossover Point Minimum Order Quantities As Technology Wafer Sizes Change, More Net Die per Wafer History Repeats Itself Cyclone Applications Consumer Market