山东农业大学《集成电路设计基础》20 静态时序分析.pptVIP

源同步时钟 流水线 几个时序参数 理想情况下的时序分析 非理想时钟 时钟不理想因素 时钟偏差(Skew) 同一时间点上，不同空间方位的时钟沿的变动, tSK 时钟抖动(Jitter) 同一点上相继的时钟沿随时间的变动; 周期到周期(短期) tJS 时钟偏差skew和抖动jitter * 电子与通信工程系 * 静态时序分析是基于路径的 路径1：模块输入端口（PI）到内部时序单元的数据输入端。 路径2：内部时序单元的时钟输入端到下一个内部时序单元的数据输入端。 路径3：内部时序单元的时钟输入端到模块输出端口（PO）。 路径4：模块输入端口（PI）到模块输出端口（PO），也称为贯通（feed-though）。 * Path Analysis Types Three types of Paths: Clock Path Data Path 异步复位/置位路径* Clock Path Async Path Data Path Async Path D Q CLR PRE D Q CLR PRE Two types of Analysis: 同步信号的分析 – clock data paths 2. 异步复位/置位的分析 – clock async paths * Launch caputure Edges CLK Launch Edge caputure Edge Data Valid DATA Launch Edge: the edge which “launches” the data from source register Caputure Edge:the edge which “capture” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle) * Setup Hold（建立/保持时间） Setup: The minimum time data signal must be stable BEFORE clock edge Hold: The minimum time data signal must be stable AFTER clock edge D Q CLR PRE CLK Th Valid DATA Tsu CLK DATA Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable. * Data Arrival Time Data Arrival Time = launch edge + Tclk1 + Tco +Tdata CLK REG1.CLK Tclk1 Data Valid REG2.D Tdata Launch Edge Data Valid REG1.Q Tco The time for data to arrive at destination register’s D input REG1 PRE D Q CLR REG2 PRE D Q CLR Comb. Logic Tclk1 TCO Tdata Data Required Time - Setup Data Required Time = Clock Arrival Time - Tsu Clock Arrival Time = capture edge+ Tclk2 capture edge = launch edge + Tcycle Data Required Time = launch edge+ Tcycle + Tclk2 - Tsu CLK REG2.CLK Tclk2 capture Edge Tsu Data Valid REG2.D REG1 PRE D Q CLR REG2 PRE D Q CLR Comb. Logic Tclk2 Tsu * Tclk2 Setup Slack REG2.CLK The margin by which the setup timing requirement is met. It ensures launched data arrives in time to meet the capturing requirement. Tsu CLK REG1.CLK Tclk1 Data Valid REG2