电连接器-高频分析-实战演示.pptVIP

Page * How to Interpret the Electrical Signal Integrity Report Signal Integrity Analysis of Straddle Type PCI Express Connector Introduction This report is for analyzing the signal integrity of the straddle type PCI express connector for Wistron‘s request. The connector model was provide by #########. I used Ansoft/Q3D to analyze a 20-pin simplified connector model and get the SPICE model of it. Then, a SPICE simulation was used to get both time domain’s ( 75ps, 150ps, 300 ps risetime ) and frequency domain’s ( 500MHz ~ 3GHz) signal integrity performance ( differential impedance, propagation delay, insertion loss, return loss, and crosstalk ) of the connector. In this report, only the connector, without the motherboard and the module PCB, was analyzed. Software we used The SI spec. we analyzed The risetime of signal is critical to the time domain performance. time voltage UI: Unit interval VH VL Tr: rise time Tf: fall time UI, also called bit time, = “1/ data rate (bps)” Risetime and falltime are usually measured between 10% and 90% of the pulse magnitude. Sometimes 20% and 80% are used. Slower Rise time Faster Rise time The faster the rise time is, the more impedance mismatch will be seen. Ansoft Analysis Model Housing : PA6T (Er = 4.0) The dielectric constant will affect the capacitance of contacts. Choose the interested area according to the pin assignment. Modify the contact model to be in the deflected state. Simplify the 3D model to exclude all arc sections (chamfers, fillets,…). Modify the arc into polylines. The contact and housing models must have no interference. 3D model pre-processing is needed to for meshing. SPICE Simulation According to the pinout of the PCI express, the following pin assignment was used to do the SPICE simulation. S5 S6 G G S7 S8 G G S9 S10 G G S1 S2 G G S3 S4 G G Pinout SPICE model of the connector * The terminator resistors are all 50 ohms. * The crosstalk between (S1,S2) a