FPGA-ARM通信代码.docVIP

library?ieee; use?ieee.std_logic_1164.all; use?ieee.std_logic_arith.all; use?ieee.std_logic_unsigned.all; ----FPGA内部寄存器地址定义： package??interface?is constant?addr_reg1?:?std_logic_vector(9?downto?0)?:=?0000000000; constant?addr_reg2?:?std_logic_vector(9?downto?0)?:=?0000000001; constant?addr_reg3?:?std_logic_vector(9?downto?0)?:=?0000000010; constant?addr_reg4?:?std_logic_vector(9?downto?0)?:=?0000000011; end; library?ieee; use?ieee.std_logic_1164.all; use?ieee.std_logic_arith.all; use?ieee.std_logic_unsigned.all; use?work.interface.all; entity?arm_fpga?is port( mcudata?:?inout?std_logic_vector(7?downto?0);--8位数据 mcuaddress?:?in?std_logic_vector(9?downto?0);--10位地址 wr?:?in?std_logic;--写信号 rd?:?in?std_logic; cs?:?in?std_logic; led?:?out?std_logic_vector(7?downto?0)); end; architecture??armfpga?of?arm_fpga?is signal??addresstemp?:?std_logic_vector(9?downto?0);--内部寄存器 signal??datatemp1,?datatemp2,?datatemp3,?datatemp4?:?std_logic_vector(7?downto?0); signal??wr_en,rd_en?:?std_logic;--读写使能 begin addresstemp?=?mcuaddress; wr_en?=?(wr?and?rd)?or?wr; rd_en?=?(wr?and?rd)?or?rd; --ARM写数据到FPGA： process(wr,wr_en) begin if??wrevent?and?wr?=?0?then if?cs?=?0and??wr_en?=?0?then case?addresstemp?is when?addr_reg1?= datatemp1?=?mcudata; when?addr_reg2?= datatemp2?=?mcudata; when?addr_reg3?= datatemp3?=?mcudata; when?addr_reg4?= datatemp4?=?mcudata; when?others?=?null; end?case; end?if; end?if; end?process; --ARM从FPGA读取数据： process(rd,rd_en) begin if??rdevent?and?rd?=?0??then if?cs?=?0?and?rd_en?=?0?then case?addresstemp?is when?addr_reg1?= mcudata?=?datatemp1; when?addr_reg2?= mcudata?=?datatemp2; when?addr_reg3?= mcudata?=?datatemp3; when?addr_reg4?= mcudata?=?datatemp4; when?others?=?null; end?case; end?if; end?if; end?process; led?=?mcudata;?--验证传输数据，LED显示 end; --?mcufpga.vhd library?ieee; use?ieee.std_logic_1164.all; use?ieee.std_logic_arith.all; use?ieee.std_logic_unsigned.all; ----FPGA内部寄存