ad9361射频和基带锁相环用户手册教案.pdfVIP

AD9361 RF and BB PLL Synthesizer User Guide ADI Confidential AD9361 RF and BB PLL Synthesizer User Guide GENERAL DESCRIPTION The AD9361 transceiver contains two identical RFPLL synthesizers to generate the required LO signals. One is programmed for the RX channel and the other for the TX channel. The transceiver also contains a BBPLL synthesizer to generate the required sampling and internal operational clocks. The PLL synthesizers are all of fractional鈥揘 architecture with completely integrated VCOs and loop filters. They require no external parts to cover the entire frequency range of the device. This configuration allows the use of any convenient reference frequency for operation on any channel with any sample rate. For FDD operation, the frequency of TX and RX can be different and both RFPLL synthesizers operate simultaneously. For TDD operation, the RFPLL synthesizers alternately turn on as appropriate for RX and TX frames. REVISION HISTORY 3/11鈥?.0 Distribution 4/11鈥?.1 Edit formatting add table. Applies to R1 version. 6/11鈥?.0 Update fixed writes for R2. Add Fast Lock info, Ext LO. 9/11鈥?.1 Include FDD and TDD tables for R2. Add BBPLL section. Examples updated. 10/11鈥?.2 Fixed typos. 11/11鈥?.3 Clarified BBPLL loop filter table value usage 1/12鈥?.4 Added how to generate TDD script with FDD calibrations to TDD MODE 鈥 Faster Lock Times section. Rev 2.4. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. lic