北邮 VHDL时序逻辑电路设计部分实验VHDL源代码.docVIP

（写的有点简陋，见谅哈,各位~~） VHDL时序设计逻辑电路设计（一） 四位二进制减计数器（摘自网上） library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count1 is port (ci:in std_logic; --计数信号 reset: in std_logic; --异步复位 load: in std_logic; --同步置数 clk: in std_logic; d : in std_logic_vector(3 downto 0); --置数值 q : buffer std_logic_vector(3 downto 0); co: out std_logic --计数溢出标志 ); end count1; architecture behave of count1 is begin process(clk,reset) begin if(reset=0) then q=0000; elsif(clkevent and clk=1) then if(load=1) then q=d; elsif(ci=1) then if(q=0) then q=1111; co=1; else q=q-1; co=0; end if; end if; end if; end process; end behave; VHDL时序设计逻辑电路设计（二） （一）带异步复位的4位能自动启动环形计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HUANXINGJISHU IS PORT(clk,rs:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END HUANXINGJISHU; ARCHITECTURE behave OF HUANXINGJISHU IS SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(rs,clk) BEGIN IF rs=0 THEN Q=0011; ELSIF(clkevent AND clk=1) THEN CASE Q IS WHEN0000=Q=0001; WHEN0001=Q=0010; WHEN0010=Q=0100; WHEN0011=Q=0110; WHEN0100=Q=1000; WHEN0101=Q=1010; WHEN0110=Q=1100; WHEN0111=Q=1110; WHEN1000=Q=0001; WHEN1001=Q=0010; WHEN1010=Q=0100; WHEN1011=Q=0110; WHEN1100=Q=1000; WHEN1101=Q=1010; WHEN1110=Q=1100; WHEN1111=Q=1110; WHEN OTHERS =Q=0000; END CASE; END IF; END PROCESS; countout=Q; END behave; （二）带异步复位的4位能自启动扭形计数器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY NIUHUAIJISHU IS PORT(clk,rs:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END NIUHUAIJISHU ; ARCHITECTURE behave OF NIUHUA